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INTEGRATED CIRCUITS
74F74 Dual D-type flip-flop
Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12
Philips Semiconductors
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
FEATURE
* Industrial temperature range available (-40C to +85C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. TYPE 74F74 TYPICAL fmax 125MHz
PIN CONFIGURATION
RD0 D0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1
SF00045
TYPICAL SUPPLY CURRENT (TOTAL) 11.5mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F74N N74F74D INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F74N I74F74D PKG. DWG. #
14-pin plastic DIP 14-pin plastic SO
SOT27-1 SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Data inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.8mA 20A/1.8mA 1.0mA/20mA
Q0, Q1, Q0, Q1 Data outputs 50/33 NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
LOGIC SYMBOL
2 12
IEC/IEEE SYMBOL
4 D0 D1 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1 11 12 13 VCC = Pin 14 GND = Pin 7 5 6 9 8 10 3
S C1
&
5
2 1
1D R
6
S C2 2D R
9
8
SF00046
SF00047
1996 Mar 12
2
853 0335 16554
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS OUTPUTS D X X X h l X Q H L H H L NC Q L H H L H NC SD L RD H L L H H H CP X X X OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Load "1" Load "0" Hold
SD
4, 10
RD
1, 13
5, 9 Q
H L H
CP
3, 11
6, 8
Q
H H
D
2, 12
VCC = Pin 14 GND = Pin 7
SF00048
NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Commercial range Operating free air temperature range Storage temperature range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIk IOH IOL Tamb b Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current O erating Operating free air tem erature range temperature Commercial range Industrial range 0 -40 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C C
1996 Mar 12
3
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -0.6 -1.8 -60 11.5 -150 16 TYP2 MAX UNIT V V V V V A A mA mA mA mA
VO OH
High-level High level output voltage
VCC = MIN VIL = MAX, VIH = MIN MIN, MAX
IO = MAX OH
VO OL VIK II IIH IIL IOS ICC
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Dn, CPn SDn, RDn
4
VCC = MIN VIL = MAX, VIH = MIN MIN, MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX
IO = MAX OL
Short-circuit output current3 Supply current (total)
NOTES: 1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2 All typical values are at VCC = 5V, Tamb = 25C. 3 Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4 Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn, RDn to Qn or Qn Waveform 1 Waveform 1 Waveform 2 100 3.8 4.4 3.2 3.5 TYP 125 5.3 6.2 4.6 7.0 6.8 8.0 6.1 9.0 MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 100 3.8 4.4 3.2 3.5 7.8 9.2 7.1 10.5 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF, RL = 500 MIN 90 3.8 4.4 3.2 2.5 8.5 9.2 7.5 10.5 MAX MHz ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, high or low Dn to CPn Hold time, high or low Dn to CPn CPn pulse width, high or low SDn, RDn pulse width, low Recovery time SDn, RDn to CPn Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 3 2.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 2.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF, RL = 500 MIN 2.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 MAX ns ns ns ns ns UNIT
1996 Mar 12
4
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
tw(L) VM
Dn
VM tsu(L)
VM th(L) 1/fmax
VM tsu(H)
VM th(H)
SDn VM
CPn
VM tw(H) tPLH
VM
tw(L)
RDn VM tPLH tPHL Qn VM tPHL
tw(L) VM tPHL VM
Qn
VM tPLH
VM tPHL
VM tPLH Qn VM VM
Qn
VM
VM
SF00050 SF01276
Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency
Waveform 2. Propagation delay for set and reset to output, set and reset pulse width
SDn or RDn
VM trec
CPn
VM
SF00051
Waveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1996 Mar 12
5
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1996 Mar 12
6
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1996 Mar 12
7
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05066
Philips Semiconductors
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